In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for CMOS applications. Traditionally, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures, the use of thick SiGe buffet layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations (TDs) and misfit dislocations, are from about 105 to about 108 defects/cm2 which are still too high for realistic VSLI (very large scale integration) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped, SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations, through the SiGe buffer layer. Various buffer structures have been used to try to increase the length of the misfit dislocation section in the structures and thereby to decrease the TD density.
In addition to the TDs that form during the relaxation process, stacking faults (SF) have been observed to form under certain strain and annealing conditions; see R. Hull and J. C. Bean, J. Vac. Sci. Technol., Vol. 7 (4), 1989, pg. 2580. It is believed that the presence of a SF defect within a semiconductor material represents a more significant threat to proper electrical behavior of the material compared to an isolated TD.
Another prior art approach, such as described in U.S. Pat. Nos. 5,461,243 and 5,759,898, both to Ek, et al., provides a structure with a relaxed and reduced defect density semiconductor layer wherein a new strain relief mechanism operates whereby the SiGe buffer layer relaxes while reducing the generation of TDs within the SiGe layer.
Co-pending and co-assigned U.S. patent application Ser. No. 10/055,138, filed Jan. 23, 2002, entitled “Method of Creating High-Quality Relaxed SiGe-On-Insulator for Strained Si CMOS Applications” provides a unique way of fabricating high-quality, substantially relaxed SiGe-on-insulator substrates. In the '138 application, a high-quality, substantially relaxed SiGe alloy layer is formed atop a first single crystal Si layer by first forming a SiGe or pure Ge layer on the surface of the first single crystal Si layer, which is present atop a barrier layer that is resistance to Ge diffusion, and then heating the layers at a temperature that permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. The heating step is performed at various temperatures and a statement is made therein that a tailored heat cycle that is based upon the melting point of the SiGe layer may be used. Specifically, the '138 application states that “the temperature is adjusted to tract below the melting point of the SiGe layer”.
The '138 application provides no specifics about the tailored heat cycle, other than the temperature is adjusted below the melting point of the SiGe. Additionally, no recognition was made in that disclosure which indicates that the tailored heat cycle could be used as a means of substantially reducing the residual defect density in the SiGe alloy layer. Moreover, the disclosure of the '138 application does not recognize that the bulk of the oxidation anneal process should be carried out at or near the melting point of SiGe. Furthermore, the disclosure of the '138 application does not recognize that the temperature of the tailored heating cycle could be adjusted so as to eliminate specific types of defects.
SGOI substrates formed using the thermal mixing process disclosed in the '138 application rely on a high-temperature oxidation to form a homogeneous SiGe alloy over an insulating layer. Under certain conditions, the surface of the SiGe alloy will begin to form micropits (i.e., microdivots) that can degrade the surface quality of the material. Inasmuch as SGOI substrates are used as a template for fabricating strained Si high-performance CMOS devices, it is imperative that the surface quality of the relaxed SiGe alloy layer be made as high as possible, in terms of smoothness and low defect density artifacts.